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參數(shù)資料
| 型號： | K7N803609B-QC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18-Bit Pipelined NtRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 378K |
| 代理商： | K7N803609B-QC25 |
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 3 -
Rev 3.0
Nov. 2003
K7N803601B
K7N801801B
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined N
t
RAM
TM
The K7N803601B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B and K7N801801B are implemented with
SAMSUNG
′
s high performance CMOS technology and is avail-
able in 100pin TQFP and Multiple power and ground pins mini-
mize ground bounce.
GENERAL DESCRIPTION
FEATURES
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
Α
interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
100-TQFP-1420A
Operating in commercial and industrial temperature range.
LOGIC BLOCK DIAGRAM
FAST ACCESS TIMES
PARAMETER
Symbol
-16
-13
Unit
Cycle Time
t
CYC
6.0
7.5
ns
Clock Access Time
t
CD
3.5
4.2
ns
Output Enable Access Time
t
OE
3.5
3.8
ns
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:17] or
A [0:18]
LBO
A
0
~A
1
A
2
~A
17
or A2~A18
256Kx36 , 512Kx18
MEMORY
ARRAY
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N803609B-QC25000 | 制造商:Samsung Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 9M-Bit 256K x 36 2.6ns 100-Pin TQFP Tray |
| K7N803645B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAMTM |
| K7N803645B-PC16000 | 制造商:Samsung SDI 功能描述: |
| K7N803645B-QC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAM |
| K7N803645B-QC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Pipelined NtRAM |
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