參數(shù)資料
型號(hào)： KAD5612P-17Q72
廠商： Intersil
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS DUAL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 405mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)差分，單極
22
FN6803.2
September 9, 2009
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to “Nap/Sleep” on
page 17). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 00h.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases.
This is particularly important when multiple ADCs are used in
a time-interleaved system. The phase slip feature allows the
rising edge of the divided clock to be advanced by one input
clock cycle when in CLK/4 mode, as shown in Figure 40.
Execution of a phase_slip command is accomplished by first
writing a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to
bit 0 at address 71h (32 sclk cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5612P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 16). This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This
register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5612P can present output data in two physical formats:
LVDS or LVCMOS. Additionally, the drive strength in LVDS
mode can be set high (3mA) or low (2mA). By default, the
tri-level OUTMODE pin selects the mode and drive level
(refer to “Digital Outputs” on page 17). This functionality can
be overridden and controlled through the SPI, as shown in
Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
0x24[7:0]
MEDIUM GAIN
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 10. POWER DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 12. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
FIGURE 40. PHASE SLIP: CLK
÷ 4 MODE, fCLOCK = 1000MHz
CLK
÷ 4
CLK
÷ 4
SLIP ONCE
CLK = CLKP - CLKN
CLK
÷ 4
SLIP TWICE
1.00ns
4.00ns
KAD5612P
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