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參數(shù)資料
| 型號： | KFG2816U1M-DED |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | OneNAND SPECIFICATION |
| 中文描述： | OneNAND的規(guī)格 |
| 文件頁數(shù)： | 42/87頁 |
| 文件大?。?/td> | 1175K |
| 代理商： | KFG2816U1M-DED |
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OneNAND128
FLASH MEMORY
42
Read Operation
The device has two read configurations ; Asynchronous read and Synchronous burst read.
The initial state machine makes the device to be automatically entered into asynchronous read mode to prevent the memory content
from spurious altering upon device power up or after a hardware reset. No commands are required to retrieve data in asynchronous
mode. The synchronous mode will be enabled by setting RM bit of System configuration1 register to Synchronous read mode.
Asynchronous Read Mode (RM = 0)
For the asynchronous read mode a valid address should be asserted on A0-A15, while driving AVD and CE to V
IL
. WE should
remain at V
IH
. The data will appear on DQ15-DQ0. Address access time (t
AA
) is equal to the delay from valid addresses to valid out-
put data. The chip enable access time(t
CE
) is the delay from the falling edge of CE to valid data at the outputs. The output enable
access time(t
OE
) is the delay from the falling edge of OE to valid data at the output.
Synchronous (Burst) Read Mode (RM = 1)
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the initial
word(t
IAA
) is output asynchronously regardless of BRL bit in System Configuration 1 register. But the host should determine BRL bit
of System configuration 1 register for the subsequent words of each burst access. The registers also can be read during burst read
mode by using AVD signal with a address. To initiate the synchronous read again, a new address during CE and AVD low toggle is
needed after the host has completed status reads or the device has completed the program or erase operation.
Continuous Linear Burst Read
The initial word(t
IAA
) is output asynchronously regardless of BRL bit in System Configuration 1 register.
Subsequent words are output
t
BA
after the rising edge of each successive clock cycle, which automatically increments the internal address counter. The RDY output
indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around after it
reaches the designated location(See Figure 12 for address map information) until the system asserts CE high, RP low or AVD low in
conjunction with a new address. The cold/warm/hot reset or asserting CE high or WE low pulse terminate the burst read operation.
If the device is accessed synchronously while it is set to asynchronous read mode, it is possible to read out the first data without prob-
lems.
Division
Add.map(word order)
BootM(0.5Kw)
0000h~01FFh
Buffer0
BufM 0(0.5Kw)
0200h~03FFh
BufM 1(0.5Kw)
0400h~05FFh
Buffer1
Reserved Main
0600h~7FFFh
N/A Reg.
BootS(16w)
8000h~800Fh
Buffer0
BufS 0(16w)
8010h~801Fh
BufS 1(16w)
8020h~802Fh
Buffer1
Reserved Spare
8030h~8FFFh
N/A Reg.
Reserved Reg.
9000h~EFFFh
Register(4Kw)
F000h~FFFFh
Reg.
Not Support
Not Support
Not Support
Figure 12. The boundary of synchronous read
* Reserved area is not available on Synchronous read
相關PDF資料 |
PDF描述 |
|---|---|
| KFG2816U1M-DIB | OneNAND SPECIFICATION |
| KFG2816U1M-DID | OneNAND SPECIFICATION |
| KFG2816U1M-PEB | OneNAND SPECIFICATION |
| KFG2816U1M-PED | OneNAND SPECIFICATION |
| KFG2816U1M-PIB | OneNAND SPECIFICATION |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KFG2816U1M-DIB | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:OneNAND SPECIFICATION |
| KFG2816U1M-DID | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:OneNAND SPECIFICATION |
| KFG2816U1M-PEB | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:OneNAND SPECIFICATION |
| KFG2816U1M-PED | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:OneNAND SPECIFICATION |
| KFG2816U1M-PIB | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:OneNAND SPECIFICATION |
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