![](http://datasheet.mmic.net.cn/300000/KFG1G1612M-DEB5_datasheet_16197847/KFG1G1612M-DEB5_50.png)
OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
50
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
This Read/Write register describes the operation of the MuxOneNAND interface.
Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT reg-
ister.) After any command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h
may be accepted during busy state of some operations. Refer to the rightmost column of the command register table below.)
F220h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
NOTE
:
1) 0080h programs both main and spare area, while 001Ah programs only spare area. Refer to chapter 5.8 for NOP limits in issuing these commands.
When using 0080h and 001Ah command, Read-only part in spare area must be masked by FF. (Refer to chapter 2.7.2)
2) ’Reset OneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state as the warm reset(=reset by RP pin).
CMD
Operation
Acceptable
command
during busy
0000h
Load single/multiple sector data unit into buffer
00F0h, 00F3h
0013h
Load single/multiple spare sector into buffer
00F0h, 00F3h
0080h
Program single/multiple sector data unit from buffer
1)
00F0h, 00F3h
001Ah
Program single/multiple spare data unit from buffer
00F0h, 00F3h
001Bh
Copy back Program operation
00F0h, 00F3h
0023h
Unlock NAND array a block
-
002Ah
Lock NAND array a block
-
002Ch
Lock-tight NAND array a block
0071h
Erase Verify Read
00F0h, 00F3h
0094h
Block Erase
00F0h, 00F3h
0095h
Multi-Block Erase
00F0h, 00F3h
00B0h
Erase Suspend
-
0030h
Erase Resume
00F0h, 00F3h
00F0h
Reset NAND Flash Core
-
00F3h
Reset OneNAND
2)
-
0065h
OTP Access
00F0h, 00F3h
2.8.18 Command Register F220h (R/W)