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參數(shù)資料
| 型號： | KFW1G16D2M-DEB5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY(54MHz) |
| 中文描述： | 閃存（54MHz之間） |
| 文件頁數(shù)： | 73/125頁 |
| 文件大小： | 1657K |
| 代理商： | KFW1G16D2M-DEB5 |
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OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
73
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
The device is designed to offer protection from any involuntary program/erase during power-transitions.
An internal voltage detector disables all functions whenever Vcc is below POR level, about 1.3V. It is recommended that the RP pin,
which provides hardware protection, should be kept at VIL before power-down.
3.6 Load Operation
See Timing Diagram 6.8
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in
order to initiate the load.
During a Load operation, the device:
-Transfers the data from NAND Flash array into the BufferRAM
-ECC is checked and any detected and corrected error is reported in the status response as well as
any unrecoverable error.
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read
from the BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation
can be checked by the host if required.
The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 2KB in size. Each DataRAM buffer has 4
Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to
the other data buffer. Refer to the information for more details in section 3.12.1, "Read-While-Load Operation".
Load Operation Flow Chart Diagram
Start
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Select DataRAM for DDP
Add: F101h DQ=DBS
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0
NO
YES
* DBS, DFS is for DDP
Host reads data from
DataRAM
Read completed
Map Out
Write 0 to interrupt register
Add: F241h DQ=0000h
3.5 Data Protection During Power Down Operation
See Timing Diagram 6.15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KFW1G16D2M-DEB6 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED5 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED6 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DIB5 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DIB6 | FLASH MEMORY(54MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KFW1G16D2M-DEB6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW1G16D2M-DIB5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW1G16D2M-DIB6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
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