參數(shù)資料
型號： KFW2G16U2M-DID6
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： FLASH MEMORY(54MHz)
中文描述： 閃存（54MHz之間）
文件頁數(shù)： 58/125頁
文件大?。?/td> 1657K
代理商： KFW2G16U2M-DID6
OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
58
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
This Read/Write register shows status of the OneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Reserved(0000000)
RI
WI
EI
RSTI
Reserved(0000)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes
low if INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Status
Conditions
Default State
Valid
State
Interrupt
Function
Cold
Warm/hot
1
1
0
off
sets itself to ’1’
One or more of RI, WI, RSTI and EI is set to ’1’,
or 0065h, 0023h, 0071h, 002A and 002C com-
mands are completed
0
→
1
Pending
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
1
→
0
off
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Status
Conditions
Default State
Valid
State
Interrupt
Function
Cold
Warm/hot
1
0
0
off
sets itself to ’1’
At the completion of an Load Operation
(0000h, 0013h, Load Data into Buffer,
or boot is done)
0
→
1
Pending
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
1
→
0
off
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Status
Conditions
Default State
Valid
State
Interrupt
Function
Cold
Warm/hot
0
0
0
off
sets itself to ’1’
At the completion of an Program Operation
(0080h, 001Ah, 001Bh)
0
→
1
Pending
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
1
→
0
off
2.8.22 Interrupt Status Register F241h (R/W)
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