- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373129 > KFW2G16U2M-DID6 (SAMSUNG SEMICONDUCTOR CO. LTD.) FLASH MEMORY(54MHz) PDF資料下載
參數(shù)資料
| 型號(hào)： | KFW2G16U2M-DID6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY(54MHz) |
| 中文描述： | 閃存（54MHz之間） |
| 文件頁(yè)數(shù)： | 68/125頁(yè) |
| 文件大?。?/td> | 1657K |
| 代理商： | KFW2G16U2M-DID6 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)當(dāng)前第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)
OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
68
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
3.3.2 Warm Reset Mode Operation
See Timing Diagrams 6.12
A Warm Reset means that the host resets the device by using the RP pin. When the a RP low is issued, the device logic stops all cur-
rent operations and executes internal reset operation and resets current NAND Flash core operation synchronized with the
falling edge of RP.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status.
The BufferRAM data is kept unchanged after Warm/Hot reset operations.
The device guarantees the logic reset operation in case RP pulse is longer than tRP min. (200ns).
The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
Warm reset will abort the current NAND Flash core operation. During a warm reset, the content of memory cells being altered is no
longer valid as the data will be partially programmed or erased.
Warm reset has no effect on contents of BootRAM and DataRAM.
3.3.3 Hot Reset Mode Operation
See Timing Diagram 6.13
A Hot Reset means that the host resets the device by Reset command. The reset command can be either Command based or
Register Based. Upon receiving the Reset command, the device logic stops all current operation and executes an internal reset
operation and resets the current NAND Flash core operation.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The
BufferRAM data is kept unchanged after Warm/Hot reset operations.
Hot Reset will abort the current NAND Flash core operation. During a Hot Reset, the content of memory cells being altered is no
longer valid as the data will be partially programmed or erased.
Hot reset has no effect on contents of BootRAM and DataRAM.
3.3.4 NAND Flash Core Reset Mode Operation
See Timing Diagram 6.14
The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command. NAND Flash core reset will
abort the current NAND Flash core operation. During a NAND Flash core reset, the content of memory cells being altered is no longer
valid as the data will be partially programmed or erased.
NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM nor register values.
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal.
This triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from
the beginning of memory into the BootRAM. This sequence is the Cold Reset of OneNAND.
The POR(Power On Reset) triggering level is typically 1.5V. Boot code copy operation activates 400us after POR.
Therefore, the system power should reach 1.7V within 400us from the POR triggering level for bootcode data to be valid.
It takes approximately 70us to copy 1KB of bootcode. Upon completion of loading into the BootRAM, it is available to be read by the
host. The INT pin is not available until after IOBE = 1 and IOBE bit can be changed by host.
3.3.1 Cold
Reset Mode Operation
See Timing Diagram 6.11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KFW1G1612M-DED5 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DEB5 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DEB6 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED5 | FLASH MEMORY(54MHz) |
| KFW1G16D2M-DED6 | FLASH MEMORY(54MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KFW-375 | 制造商:WALDOM ELECTRONICS 功能描述: |
| KFW-376 | 制造商:WALDOM ELECTRONICS 功能描述: |
| KFW-377 | 制造商:WALDOM ELECTRONICS 功能描述: |
| KFW-379 | 制造商:GC Electronics 功能描述:Washers Flat Fiber 0.375in 0.625in 0.0313in 3/8 Screw Size |
| KFW4G1612M-DEB5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。