OPERATIONAL MODES FUNCTIONAL DEVICE OPERATIO" />
參數(shù)資料
型號(hào): KIT33972AEWEVBE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 5/32頁(yè)
文件大?。?/td> 0K
描述: KIT EVALUATION FOR MC33972
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,開(kāi)關(guān)探測(cè)
嵌入式:
已用 IC / 零件: MC33972
主要屬性: 8 可編程輸入(電池開(kāi)關(guān)或接地開(kāi)關(guān))
次要屬性: 14 開(kāi)關(guān)至接地輸入
已供物品: 板,CD
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33972
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MCU INTERFACE DESCRIPTION
The 33972 device directly interfaces to a 3.3 or 5.0 V
microcontroller unit (MCU). SPI serial clock frequencies up to
6.0 MHz may be used for programming and reading switch
input status (production tested at 4.16 MHz). Figure 8
illustrates the configuration between an MCU and one 33972.
Serial peripheral interface (SPI) data is sent to the 33972
device through the SI input pin. As data is being clocked into
the SI pin, status information is being clocked out of the
device by the SO output pin. The response to a SPI
command will always return the switch status, interrupt flag,
and thermal flag. Input switch states are latched into the SO
register on the falling edge of the chip select (CS) pin.
Twenty-four bits are required to complete a transfer of
information between the 33972 and the MCU.
Figure 8. SPI Interface with Microprocessor
Two or more 33972 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial. Figures 9 and 10 show the configurations. When using
the serial configuration, 48-clock cycles are required to
transfer data in/out of the ICs.
Figure 9. SPI Parallel Interface with Microprocessor
Figure 10. SPI Serial Interface with Microprocessor
33972
MC68HCXX
Microcontroller
Receive
Buffer
Parallel
Ports
To Logic
24-Bit Shift Register
Shift Register
MOSI
SI
MISO
SO
SCLK
CS
INT
Parallel
Ports
MC68HCXX
Microcontroller
33972
SI
SCLK
CS
INT
SI
SO
SCLK
CS
INT
SCLK
MISO
MOSI
Shift Register
SO
Parallel
Ports
MC68HCXX
Microcontroller
33972
SI
SCLK
CS
INT
SI
SO
SCLK
CS
INT
SO
INT
SCLK
MISO
MOSI
Shift Register
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