參數(shù)資料
型號(hào): KM416C254D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256K x 16Bit CMOS Dynamic RAM with Extended Data Out
中文描述: 256 × 16Bit的CMOS動(dòng)態(tài)RAM的擴(kuò)展數(shù)據(jù)輸出
文件頁數(shù): 8/36頁
文件大小: 840K
代理商: KM416C254D
KM416C254D, KM416V254D
CMOS DRAM
t
ASC
,
t
CAH
are referenced to the earlier CAS rising edge.
t
CP
is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word red-modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to earlier CAS falling low before RAS transition low.
t
CHR
is referenced to the later CAS rising high after RAS transition low.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
DQ0 ~ DQ15
Din
20.
18.
17.
16.
13.
15.
14.
19.
UCAS
W
t
DS
, t
DH
are specified for the earlier CAS falling low.
f
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms
before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
21.
22.
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