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參數(shù)資料
| 型號(hào)： | KM432S2030CT-F6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL |
| 文件頁(yè)數(shù)： | 8/43頁(yè) |
| 文件大?。?/td> | 1161K |
| 代理商： | KM432S2030CT-F6 |
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KM432S2030C
CMOS SDRAM
REV. 1.1 Mar. '99
- 8 -
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-6
-7
-8
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
6
1000
7
1000
8
1000
10
1000
ns
1
CAS Latency=2
-
-
10
12
CLK to valid
output delay
CAS Latency=3
t
SAC
-
5.5
-
5.5
-
6
-
7
ns
1, 2
CAS Latency=2
-
-
-
-
-
7
-
8
Output data
t
OH
2.5
-
2.5
-
2.5
-
2.5
-
ns
2
CLK high pulse width
CAS Latency=3
t
CH
2.5
-
3
-
3
-
3.5
-
ns
3
CAS Latency=2
-
CLK low pulse width
CAS Latency=3
t
CL
2.5
-
3
-
3
-
3.5
-
ns
3
CAS Latency=2
-
Input setup time
CAS Latency=3
t
SS
1.5
-
1.75
-
2
-
2.5
-
ns
3
CAS Latency=2
-
-
Input hold time
t
SH
1
-
1
-
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
1
-
1
-
ns
2
CLK to output
in Hi-Z
CAS Latency=3
t
SHZ
-
5.5
-
5.5
-
6
-
7
ns
CAS Latency=2
-
-
-
-
-
7
-
8
Symbol
Version
Unit
-6
-7
-8
-10
CL
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC
(
min
)
3
6
-
-
3
7
-
-
3
8
2
10
3
2
CLK
ns
CLK
CLK
CLK
CLK
us
CLK
10
12
2
3
3
7
-
-
-
3
3
7
-
-
-
3
3
6
2
2
5
2
2
5
2
2
4
100
11
-
10
-
9
7
7
6
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV"
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM432S2030CT-F7 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F8 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CTG10 | 制造商:SAMSUNG 功能描述:* |
| KM432S2030CT-G10 | 制造商:Samsung SDI 功能描述:DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II |
| KM432S2030CT-G6 | 制造商:Samsung Semiconductor 功能描述: |
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