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參數(shù)資料
| 型號： | KM44L32031BT-G(L)Z |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 1.0 |
| 中文描述： | DDR SDRAM的規(guī)范版本1.0 |
| 文件頁數(shù)： | 43/53頁 |
| 文件大?。?/td> | 669K |
| 代理商： | KM44L32031BT-G(L)Z |
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- 43 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
1
2
3
4
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.62
0.5*VDDQ-0.2
Note 1. Vih(max) = 4.2V. The overshoot voltage duration is
≤
3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is
≤
3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
Table 13. AC operating conditions
I
DD7
: Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM44L32031BT-GLZ/Y/0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0 |
| KM44S16020CT-G10 | 制造商:SEC 功能描述: |
| KM44S32030 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 4Bit x 4 Banks Synchronous DRAM |
| KM44S32030B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL |
| KM44S32030BT-G/F10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL |
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