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參數(shù)資料
| 型號： | KM44S64230A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16M x 4Bit x 4 Banks Synchronous DRAM(16M x 4位 x 4組同步動態(tài)RAM) |
| 中文描述： | 16米x 4位× 4銀行同步DRAM（16米x 4位× 4組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | KM44S64230A |
KM44S64230A
CMOS SDRAM
REV. 0 May '98
Preliminary
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-8
-H
-L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
125
110
110
110
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
1
mA
I
CC2
PS
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
15
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
4
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
3
mA
I
CC3
PS
3
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
25
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
15
mA
Operating current
(Burst mode)
I
CC4
I
OL
= 0 mA
Page burst
t
CCD
= 2CLKs
3
125
105
105
105
mA
1
2
95
105
95
90
mA
1
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
180
160
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
2
mA
3
1
mA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM44S64230AT-G**
4. KM44S64230AT-F**
Notes :
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