參數(shù)資料
型號(hào): KM48V2004C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出))
中文描述: 200萬× 8位的擴(kuò)展數(shù)據(jù)輸出的CMOS動(dòng)態(tài)RAM(2米× 8位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器(帶擴(kuò)展數(shù)據(jù)輸出))
文件頁數(shù): 7/21頁
文件大?。?/td> 367K
代理商: KM48V2004C
KM48C2004C, KM48C2104C
KM48V2004C, KM48V2104C
CMOS DRAM
TEST MODE CYCLE
Parameter
Symbol
-5
-6
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
RAS
t
CAS
t
RSH
t
CSH
t
RAL
t
CWD
t
RWD
t
AWD
t
CPWD
t
HPC
t
HPRWC
t
RASP
t
CPA
t
OEA
t
OED
t
OEH
89
109
ns
Read-modify-write cycle time
121
145
ns
Access time from RAS
55
65
ns
3,4,10,12
Access time from CAS
18
20
ns
3,4,5,12
Access time from column address
30
35
ns
3,10,12
RAS pulse width
55
10K
65
10K
ns
CAS pulse width
13
10K
15
10K
ns
RAS hold time
18
20
ns
CAS hold time
43
50
ns
Column address to RAS lead time
30
35
ns
CAS to W delay time
35
39
ns
7
RAS to W delay time
72
84
ns
7
Column address to W delay time
47
54
ns
7
CAS precharge to W delay time
52
59
ns
Hyper Page cycle time
25
30
ns
13
Hyper Page read-modify-write cycle time
53
61
ns
13
RAS pulse width (Hyper Page cycle)
55
200K
65
200K
ns
Access time from CAS precharge
33
40
ns
3
OE access time
18
20
ns
OE to data delay
18
20
ns
OE command hold time
18
20
ns
( Note 11 )
相關(guān)PDF資料
PDF描述
KM48C2004C 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出))
KM48C2104C 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出))
KM48V2104C 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出))
KM48V8004B 8M x 8bit CMOS Dynamic RAM with Extended Data Out
KM48V8104B 8M x 8bit CMOS Dynamic RAM with Extended Data Out
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參數(shù)描述
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