參數(shù)資料
型號: KM68512ALG-7L
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2.7 V to 5.5 V, <100 &#181;A, 8-Bit nanoDAC&reg; D/A Converter with I2C Compatible Interface, Tiny SC70 Package; Package: SC70; No of Pins: 6; Temperature Range: Industrial
中文描述: 64Kx8位低功耗CMOS靜態(tài)RAM
文件頁數(shù): 2/9頁
文件大小: 143K
代理商: KM68512ALG-7L
KM68512A Family
CMOS SRAM
Revision 4.0
January 1997
2
64Kx8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
The KM68512A families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
Process Technology: Poly Load
Organization: 64Kx8
Power Supply Voltage: 4.5~5.5V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL Compatible
Package Type: 32-SOP-525, 32-TSOP1-0820F
PIN DESCRIPTION
Name
Function
CS
1
, CS
2
Chip Select Inputs
OE
Output Enable Input
WE
Write Enable Input
A
0
~A
15
Address Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Power
Vss
Ground
N.C
No Connection
PRODUCT FAMILY
Product Family
Operating Temperature
V
CC
Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
100
μ
A
20
μ
A
100
μ
A
50
μ
A
Operating
(I
CC2
, Max)
KM68512AL
Commercial (0~70
°
C)
4.5 to 5.5V
55/70ns
70mA
32-SOP
32-TSOP1-F
KM68512AL-L
KM68512ALI
Industrial (-40~85
°
C)
70ns
KM68512ALI-L
FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP
Type1 - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N.C
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-SOP
N.C
Precharge circuit.
Memory array
512 rows
128
×
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1
A2
A8
A9
A11
A10
A3
A4
A5
A6
A7
A12
A14
CS1
CS2
WE
OE
I/O1
Data
cont
Data
cont
I/O8
A13
A15
Control
Logic
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