參數(shù)資料
型號： KM68FR1000
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128K x8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(128K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
中文描述： 128K的x8位超低功耗和低電壓的CMOS全靜態(tài)RAM（128K的× 8位超低功耗和低電壓的CMOS靜態(tài)RAM）的
文件頁數(shù)： 8/11頁
文件大小： 207K
代理商： KM68FR1000
Revision 3.0
July 1998
CMOS SRAM
KM68FV1000, KM68FS1000, KM68FR1000 Family
8
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
3.0/2.7/2.3/1.8V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
≥
V
CC
-0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
1
Controlled)
Address
CS
1
t
AW
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low: A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
CS
2
t
WP(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
3.0/2.7/2.3/1.8V
CS
2
0.4V
GND
V
DR
Data Retention Mode
t
SDR
t
RDR
CS
2
≤
0.2V
相關(guān)PDF資料
PDF描述
KM68FS1000 128K x8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(128K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
KM68FV1000 128K x8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(128K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
KM68FR2000 256Kx8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(256K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
KM68FS2000 256Kx8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(256K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
KM68FV2000 256Kx8 Bit Super Low Power and Low Voltage Full CMOS Static RAM(256K x 8位超低功耗和低電壓CMOS 靜態(tài) RAM)
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