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參數(shù)資料
| 型號： | KM68V1002CLIT-15 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.400 INCH, TSOP2-32 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 183K |
| 代理商： | KM68V1002CLIT-15 |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 2.0
- 5 -
March 1999
PRELIMINARY
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM68V1002C/CL-12
KM68V1002C/CL-15
KM68V1002C/CL-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
8
-
9
-
10
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
tWP
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
tWP1
12
-
15
-
20
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
6
-
7
-
8
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
CS
Address
OE
Data out
tAA
tOLZ
tLZ(4,5)
tOH
tOHZ
tRC
tOE
tCO
tPU
tPD
Valid Data
tHZ(3,4,5)
50%
VCC
Current
ICC
ISB
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