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參數(shù)資料
| 型號(hào)： | KM68V1002CLIT-15 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.400 INCH, TSOP2-32 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 183K |
| 代理商： | KM68V1002CLIT-15 |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 2.0
- 7 -
March 1999
PRELIMINARY
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
Address
CS
tAW
tDW
tDH
Data Valid
WE
Data in
Data out
High-Z
High-Z(8)
tCW(3)
tWP(2)
tAS(4)
tWC
tWR(5)
High-Z
tLZ
tWHZ(6)
FUNCTIONAL DESCRIPTION
* X means Don
′t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
X
Write
DIN
ICC
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