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參數(shù)資料
| 型號： | KM718V089T-60 |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 CACHE SRAM, 3.5 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 536K |
| 代理商： | KM718V089T-60 |
512Kx36 & 1Mx18 Synchronous SRAM
- 18 -
Rev 1.0
December 1999
KM718V089
KM736V989
APPLICATION INFORMATION
DEPTH EXPANSION
Data
Address
CLK
ADS
Microprocessor
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV
ADSP
1Mx18
SPB
SRAM
(Bank 0)
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV
ADSP
1Mx18
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A[0:20]
A[20]
A[0:19]
A[20]
A[0:19]
I/O[0:71]
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
tSS
tSH
Don
′t Care
A1
A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1)
Q2-2
Q2-4
Q2-3
tAS
tAH
tWS
tWH
tADVS
tADVH
tOE
tLZOE
tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tCSS
tCSH
tCD
tLZC
[0:n]
Undefined
Q2-1
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth ,
17 256K depth
18 512K depth ,
19 1M depth
20 2M depth
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