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參數(shù)資料
| 型號(hào)： | KM718V987 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 Synchronous SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 536K |
| 代理商： | KM718V987 |
512Kx36 & 1Mx18 Synchronous SRAM
- 2 -
Rev 1.0
December 1999
KM718V089
KM736V989
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
The KM736V989 and KM718V089 are 18,874,368-bit Syn-
chronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 512K(1M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache control-
ler(ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system
′
s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The KM736V989 and KM718V089 are fabricated using
SAMSUNG
′
s high performance CMOS technology and is
available in a 100pin TQFP and 119BGA package. Multiple
power and ground pins are utilized to minimize ground
bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V +0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear
burst.
Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
512Kx36 , 1Mx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~A
′
1
A
0
~A
1
or A
2
~A
19
or A
0
~A
19
FAST ACCESS TIMES
PARAMETER
Symbol -54 -60 -67 -72 -10 Unit
Cycle Time
t
CYC
5.4 6.0 6.7 7.2
10
ns
Clock Access Time
t
CD
3.3 3.5 3.8 4.0 4.5
ns
Output Enable Access Time
t
OE
3.3 3.5 3.8 4.0 4.5
ns
A
0
~A
18
A
2
~A
18
DQPa,DQPb
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