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參數資料
| 型號： | KM736FV4022 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36 Synchronous SRAM(128Kx36位同步靜態(tài) RAM) |
| 中文描述： | 128K × 36至同步SRAM（128K × 36至位同步靜態(tài)內存） |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 267K |
| 代理商： | KM736FV4022 |
PRELIMINARY
Rev 0.2
Jan. 1998
KM718FV4022
128Kx36 & 256Kx18 SRAM
- 2 -
KM736FV4022
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
Pin Description
K, K
Differential Clocks(PECL Level)
V
DDQ
Output Power Supply
SAn
Synchronous Address Input
M
1
, M
2
Read Protocol Mode Pins ( M
1
=V
DD
, M
2
=V
SS
)
DQn
Bi-directional Data Bus
G
Asynchronous Output Enable
SW
Synchronous Global Write Enable
SS
Synchronous Select
SWa
Synchronous Byte a Write Enable
TCK
JTAG Test Clock
SWb
Synchronous Byte b Write Enable
TMS
JTAG Test Mode Select
SWc
Synchronous Byte c Write Enable
TDI
JTAG Test Data Input
SWd
Synchronous Byte d Write Enable
TDO
JTAG Test Data Output
ZZ
Asynchronous Power Down
V
SS
GND
V
DD
Core Power Supply
NC
No Connection
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
128Kx36 or 256Kx18 Organizations.
3.3V Core Power Supply.
LVTTL Input and Output Levels.
Differential, PECL Clock Inputs K, K.
Synchronous Read and Write Operation
Registered Input and Latched Output
Internal Pipeline Latches to Support Late Write.
Byte Write Capability(four byte write selects, one for each 9 bits)
Synchronous or Asynchronous Output Enable.
Power Down Mode via ZZ Signal.
JTAG 1149.1 Compatible Test Access port.
119(7x17) Pin Ball Grid Array Package(14mmx22mm).
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17]
CK
SS
SW
SWx
(x=a, b, c, d)
or (x=a, b)
G
Organization
Part Number
Cycle
Time
Access
Time
128Kx36
KM736FV4022H-65
6
6.5
KM736FV4022H-7
6.5
7.0
KM736FV4022H-75
7
7.5
256Kx18
KM718FV4022H-65
6
6.5
KM718FV4022H-7
6.5
7.0
KM718FV4022H-75
7
7.5
128Kx36
or
256Kx18
Array
Data In
Register
ZZ
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
K
K
CK
R
Column Decoder
Write/Read Circuit
0 1
Data Out
Latch
1
Read
Address
Register
Write
Address
Register
Latch
SW
Register
SW
Register
Latch
SWx
Register
SWx
Register
SS
Register
SS
Register
0
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