參數(shù)資料
型號: KM736FV4022
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Kx36 Synchronous SRAM(128Kx36位同步靜態(tài) RAM)
中文描述: 128K × 36至同步SRAM(128K × 36至位同步靜態(tài)內(nèi)存)
文件頁數(shù): 7/12頁
文件大?。?/td> 267K
代理商: KM736FV4022
PRELIMINARY
Rev 0.2
Jan. 1998
KM718FV4022
128Kx36 & 256Kx18 SRAM
- 7 -
KM736FV4022
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last write
cycle address.
3. Data is valid at the output at the later of t
KHQV
following the rising clock edge, or t
KLQV
following the fallowing clock edge.
4. When SS is sampled high or SW is sampled low on the rising edge of clock, the outputs go into Hi-Z state no later than t
KHQZ
following
the rising clock edge.
5. When SS is low and SW is high on the rising edge of clock, the outputs go into Low-Z state(being driven) no earlier than t
KLQX1
following
the next falling edge of clock.
6. When the SRAM is deselected, the output goes Hi-Z at t
KHQZ
following the rising clock edge. On the next read cycle, note that the
SRAM output do not leave the Hi-Z state until t
KLQX1
after the falling clock edge.
1
2
3
4
5
6
7
8
K
SAn
SS
SW
SWx
DQn
G
A
1
A
2
A
3
A
4
A
5
A
4
A
6
A
7
Q
1
Q
2
D
3
D
4
Q
5
Q
4
t
KHKH
t
AVKH
t
KHAX
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
WVKH
t
KHWX
t
KLQV
t
KHQZ
t
WVKH
t
KHWX
t
KHQV
t
KHQZ
t
DVKH
t
KHDX
t
GHQZ
t
GLQV
t
KLQV
A
1
t
KLQX
t
KLQV
t
GLQX
t
KLQX1
t
KLQX1
9
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