參數(shù)資料
型號: KMPC8313ECZQADDB
廠商: Freescale Semiconductor
文件頁數(shù): 38/99頁
文件大小: 0K
描述: IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 267MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
9.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low-phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters for SGMII protocol.
Figure 31. Differential Measurement Points for Rise and Fall Time
Table 39. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Note
Rising edge rate
Rise edge rate
1.0
4.0
V/ns
2, 3
Falling edge rate
Fall edge rate
1.0
4.0
V/ns
2, 3
Differential input high voltage
VIH
+200
mV
2
Differential input low voltage
VIL
—–200
mV
2
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-fall matching
20
%
1, 4
Notes:
1. Measurement taken from single-ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 31.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point, where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge
rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20% of the slowest edge rate. See Figure 32.
VIH = +200 mV
VIL = –200 mV
0.0 V
SDn_REF_CLK
Minus
SDn_REF_CLK
Fall Edge Rate
Rise Edge Rage
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