參數(shù)資料
型號: KMPC8313ZQAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 37/99頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
42
Freescale Semiconductor
assumes that the LVPECL clock driver’s output impedance is 50
R1 is used to DC-bias the LVPECL
outputs prior to AC coupling. Its value could be ranged from 140
to 240 depending on the clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8313E
SerDes3 reference clock’s differential input amplitude requirement (between 200 and 800 mV differential
peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference
clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25
Consult with the clock driver chip manufacturer to verify whether this connection scheme is compatible
with a particular clock driver chip.
Figure 29. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock
input’s DC requirement.
Figure 30. Single-Ended Connection (Reference Only)
SDn_REF_CLK
Clock Driver
100
Differential PWB Trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK Driver Chip
R2
MPC8313E
10 nF
CLK_Out
R2
R1
Clock Driver
50
R1
50
SDn_REF_CLK
100
Differential PWB Trace
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
MPC8313E
33
Total 50
Assume clock driver’s
output impedance is about 16
50
SerDes Refer.
CLK Receiver
50
50
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