This table summarizes the signal impe" />
參數(shù)資料
型號: KMPC8313ZQAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 91/99頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應商設備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
91
This table summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal NVDD, 105C.
22.7
Configuration Pin Muxing
The MPC8313E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
22.8
Pull-Up Resistor Requirements
The MPC8313E requires high resistance pull-up resistors (10 k
is recommended) on open drain type pins
including I2C, and IPIC (integrated programmable interrupt controller).
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 61. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions because most have asynchronous behavior and spurious assertion,
which give unpredictable results.
Refer to the PCI 2.2 Specification, for all pull-ups required for PCI.
22.9
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in
IEEE 1149.1, but is provided on any Freescale devices that are built on Power Architecture technology.
The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, systems generally assert TRST during power-on reset. Because the
JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to PORESET is not practical.
Table 71. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(Not Including PCI
Output Clocks)
PCI Output Clocks
(Including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
RP
42 Target
25 Target
42 Target
20 Target
Z0
Differential
NA
ZDIFF
Note: Nominal supply voltages. See Table 1, TJ = 105 C.
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