參數(shù)資料
型號: KMPC8314CVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 26/101頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 620-PBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
30
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
9.3.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Input low current
IIL
NVDD = Max
VIN = 0.5 V
–600
A
Note:
1. The symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2.
Table 31. MII Management AC Timing Specifications
At recommended operating conditions with NVDD is 3.3 V ± 300 mv
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Note
MDC frequency
fMDC
—2.5
MHz
2
MDC period
tMDC
400
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO delay
tMDKHDX
10
170
ns
3
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
10
ns
MDC fall time
tMDHF
10
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the maximum frequency is 4.16 MHz and
the minimum frequency is 0.593 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).
Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V (continued)
Parameter
Symbol
Conditions
Min
Max
Unit
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