參數(shù)資料
型號(hào)： KMPC8314CVRAGDA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 40/101頁(yè)
文件大小： 0K
描述： IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC83xx
處理器類(lèi)型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤(pán)
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
43
JTAG
12.2
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface. This table
provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31.
Table 46. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1
At recommended operating conditions (see Table 2)
Parameter
Symbol 2
Min
Max
Unit
Note
JTAG external clock frequency of operation
fJTG
033.3
MHz
—
JTAG external clock cycle time
t JTG
30
—
ns
—
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
—
ns
—
JTAG external clock rise and fall times
tJTGR, tJTGF
02
ns
—
TRST assert time
tTRST
25
—
ns
3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
—
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
11
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
—
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
Note:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
load (see Table 27).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
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KMPC8315CVRAGDA 功能描述:微處理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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