參數(shù)資料
型號: KMPC8315ECVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 52/106頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
MPC8315E Features
Signal (RCK) can be configured as either input or output
Frame sync and data signals can be programmed to be sampled either on the rising edge or on the
falling edge of the clock
Frame sync can be programmed as active low or active high
Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame
MSB or LSB first support
2.7
USB Dual-Role Controller
The USB controller includes the following features:
Designed to comply with USB Specification, Rev. 2.0
Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.
Low-speed operation is supported only in host mode.
Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY
Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI PHY
2.8
Dual PCI Express Interfaces
The PCI Express interfaces have the following features:
PCI Express 1.0a compatible
x1 link width
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing
128-byte maximum payload size
Support for MSI and INTx interrupt messages
Virtual channel 0 only
Selectable Traffic Class
Full 64-bit decode with 32-bit wide windows
Dedicated descriptor based DMA engine per interface with separate read and write channels
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