參數(shù)資料
型號(hào): KMPC8349ECVVAJDB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 12/87頁(yè)
文件大小: 0K
描述: IC MPU PWRQUICC II 672-TBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 672-LBGA
供應(yīng)商設(shè)備封裝: 672-TBGA(35x35)
包裝: 托盤
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
2
Freescale Semiconductor
Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
silicon revision level determination.
1
Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8349EA.
Figure 1. MPC8349EA Block Diagram
Major features of the device are as follows:
Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
TSEC
Coherent System Bus
PCI1
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
SPI
Serial
IRQs
ROM
I2C
I2C Interfaces
TSEC
DDR/DDR2
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
DUART
e300 Core
DMA Controller
Serial Peripheral
Interface
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI2
0/32b PCI Controller
Security Engine
Arbiter Bus
Monitor
USB Hi-Speed
Host Device
General Purpose I/O
USB0
USB1
GPIO
SDRAM
DDR/DD
R2
DMA
MII, GMII, TBI,
RTBI, RGMII
10/100/1Gb
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