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    參數(shù)資料
    型號: KMPC8358EVRAGDDA
    廠商: Freescale Semiconductor
    文件頁數(shù): 20/95頁
    文件大?。?/td> 0K
    描述: IC MPU POWERQUICC II PRO 668PBGA
    標準包裝: 2
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 400MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 668-BBGA 裸露焊盤
    供應商設備封裝: 668-PBGA-PGE(29x29)
    包裝: 托盤
    MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
    Freescale Semiconductor
    27
    UCC Ethernet Controller: Three-Speed Ethernet, MII Management
    8.2
    GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
    The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
    8.2.1
    GMII Timing Specifications
    This sections describe the GMII transmit and receive AC timing specifications.
    8.2.1.1
    GMII Transmit AC Timing Specifications
    Table 26 provides the GMII transmit AC timing specifications.
    Table 25. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)
    Parameters
    Symbol
    Conditions
    Min
    Max
    Unit
    Supply voltage 2.5 V
    LVDD
    2.37
    2.63
    V
    Output high voltage
    VOH
    IOH = –1.0 mA
    LVDD = Min
    2.00
    LVDD + 0.3
    V
    Output low voltage
    VOL
    IOL = 1.0 mA
    LVDD = Min
    GND – 0.3
    0.40
    V
    Input high voltage
    VIH
    —LVDD = Min
    1.7
    LVDD + 0.3
    V
    Input low voltage
    VIL
    —LVDD = Min
    –0.3
    0.70
    V
    Input current
    IIN
    0 V
    ≤ VIN ≤ LVDD
    —±10
    μA
    Table 26. GMII Transmit AC Timing Specifications
    At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
    Parameter/Condition
    Symbol1
    Min
    Typ
    Max
    Unit
    Notes
    GTX_CLK clock period
    tGTX
    —8.0
    ns
    GTX_CLK duty cycle
    tGTXH/tGTX
    40
    60
    %
    GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
    tGTKHDX
    tGTKHDV
    0.5
    ——
    5.0
    ns
    GTX_CLK clock rise time, (20% to 80%)
    tGTXR
    ——
    1.0
    ns
    GTX_CLK clock fall time, (80% to 20%)
    tGTXF
    ——
    1.0
    ns
    GTX_CLK125 clock period
    tG125
    —8.0
    ns
    2
    GTX_CLK125 reference clock duty cycle measured at
    LVDD/2
    tG125H/tG125
    45
    55
    %
    2
    Notes:
    1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
    and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing
    (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
    the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock
    reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
    general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
    For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is
    used with the appropriate letter: R (rise) or F (fall).
    2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
    convention.
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