參數(shù)資料
型號: KMPC8360VVAHFH
廠商: Freescale Semiconductor
文件頁數(shù): 24/95頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 740-TBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 500MHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應商設備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
30
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 11 shows the MII transmit AC timing diagram.
Figure 11. MII Transmit AC Timing Diagram
8.2.2.2
MII Receive AC Timing Specifications
Table 29 provides the MII receive AC timing specifications.
Figure 12 provides the AC test load.
Figure 12. AC Test Load
Table 29. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
ns
RX_CLK clock period 100 Mbps
tMRX
—40
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise time, (20% to 80%)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time, (80% to 20%)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
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