參數(shù)資料
型號(hào): KMPC8379CVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 26/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 689-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
16
Freescale Semiconductor
Table 12 provides the PLL lock times.
6
DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.
Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—4
ns
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1—
tPCI_SYNC_IN
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 12. PLL Lock Times
Parameter
Min
Max
Unit
Note
PLL lock times
100
μs—
Note:
The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 22, “Clocking,” for more information.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
1.71
1.89
V
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V2, 5
I/O termination voltage
VTT
MVREF –0.04
MVREF +0.04
V
Input high voltage
VIH
MVREF + 0.140
GVDD +0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.140
V
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT =1.40V)
IOH
–13.4
mA
Table 11. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Note
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