參數(shù)資料
型號： KMPC8379VRALG
廠商： Freescale Semiconductor
文件頁數(shù)： 24/117頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 689-PBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 667MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
14
Freescale Semiconductor
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. This table provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
4.3
eTSEC Gigabit Reference Clock Timing
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Note
CLKIN/PCI_CLK frequency
fCLKIN
25
—
66.666
MHz
1, 6
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
40
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
CLKIN/PCI_CLK jitter
—
± 150
ps
Notes:
1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter-short term and long term-and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low
to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
Table 9. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
EC_GTX_CLK125 frequency
tG125
—
125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—8
—
ns
—
EC_GTX_CLK rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
tG125R/tG125F
——
0.75
1.0
ns
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII, RTBI
tG125H/tG125
47
—
53
EC_GTX_CLK125 jitter
—
±150
ps
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The
EC_GTX_CLK125 duty cycle can be loosened from 47%/ 53% as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications,” for the duty cycle for
10Base-T and 100Base-T reference clock.
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