參數(shù)資料
型號(hào): KMPC8555PXAQF
廠商: Freescale Semiconductor
文件頁數(shù): 38/88頁
文件大小: 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
43
CPM
10 CPM
This section describes the DC and AC electrical specifications for the CPM of the MPC8555E.
10.1
CPM DC Electrical Characteristics
Table 32 provides the DC electrical characteristics for the CPM.
10.2
CPM AC Timing Specifications
Table 33 and Table 34 provide the CPM input and output AC timing specifications, respectively.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
Table 32. CPM DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Input high voltage
VIH
2.0
3.465
V
1
Input low voltage
VIL
GND
0.8
V
1, 2
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
1
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
1
Output high voltage
VOH
IOH = –2.0 mA
2.4
V
1
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
1
Note:
1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31].
2. VIL(max) for the IIC interface is 0.8 V rather than the 1.5 V specified in the IIC standard
Table 33. CPM Input AC Timing Specifications 1
Characteristic
Symbol 2
Min3
Unit
FCC inputs—internal clock (NMSI) input setup time
tFIIVKH
6ns
FCC inputs—internal clock (NMSI) hold time
tFIIXKH
0ns
FCC inputs—external clock (NMSI) input setup time
tFEIVKH
2.5
ns
FCC inputs—external clock (NMSI) hold time
tFEIXKHb2
ns
SCC/SMC/SPI inputs—internal clock (NMSI) input setup time
tNIIVKH
6ns
SCC/SMC/SPI inputs—internal clock (NMSI) input hold time
tNIIXKH
0ns
SCC/SMC/SPI inputs—external clock (NMSI) input setup time
tNEIVKH
4ns
SCC/SMC/SPI inputs—external clock (NMSI) input hold time
tNEIXKH
2ns
TDM inputs/SI—input setup time
tTDIVKH
4ns
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