參數(shù)資料
型號(hào)： KMPC8555PXAQF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 62/88頁(yè)
文件大小： 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1.3V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
65
Package and Pin Listings
PB[18:31]
P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R7
I/0
OVDD
—
PC[0, 1, 4–29]
R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
W6, W7, W8
I/0
OVDD
—
PD[7, 14–25, 29–31]
Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
AC3, AC2, AC1, AD6, AE3, AE2
I/0
OVDD
—
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 k
Ω) be placed on this pin to OVDD.
3. TEST_SEL0 must be pulled-high, TEST_SEL1 must be tied to ground.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8555E is in
the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down resistor. If an
external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is
intended to be high during reset.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k
Ω pull-up
or pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
10. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the
PCI Specification.
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14. Internal thermally sensitive resistor.
15. No connections should be made to these pins.
16. These pins are not connected for any functional use.
17. PCI specifications recommend that a weak pull-up resistor (2–10 k
Ω) be placed on the higher order pins to OVDD when
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to
pull this signal to a logic 1 during reset.
19. Recommend a pull-up resistor (~1 k
Ω) be placed on this pin to OVDD.
20. These are test signals for factory use only and must be pulled up (100
Ω το 1kΩ) to OVDD for normal machine operation.
21. If this signal is used as both an input and an output, a weak pull-up (~
10kΩ) is required on this pin.
22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
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