參數(shù)資料
型號： KMSC7118VM1200
廠商： Freescale Semiconductor
文件頁數(shù)： 47/60頁
文件大?。?/td> 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 2
系列： StarCore
類型： 定點
接口： 主機接口，I²C，UART
時鐘速率： 300MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 464kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
Hardware Design Considerations
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
51
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
8- or 16-bit mode as specified by the H8BIT pin.
Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
3.4.3.2
I2C Boot
When the MSC7118 device is configured to boot from the I
2C port, the boot program configures the GPIO pins for I2C
operation. Then the MSC7118 device initiates accesses to the I
2C module, downloading data to the MSC7118 device. The I2C
interface is configured as follows:
PLL is disabled and bypassed so that the I
2C module is clocked with the IPBus clock.
I
2C interface operates in master mode and polling is used.
EPROM operates in slave mode.
Clock divider is set to 128.
Address of slave during boot is 0xA0.
The IPBus clock is internally divided to generate the bit clock, as follows:
CLKIN must be a maximum of 100 MHz
PLL is bypassed.
IPBus clock = CLKIN/2 is a maximum of 50 MHz.
I2C bit clock must be less than or equal to:
— IPBus clock/I2C clock divider
— 50 MHz (max)/128
— 390.6 KHz
This satisfies the maximum clock rate requirement of 400 kbps for the I2C interface. For details on the boot procedure, see the
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3
SPI Boot
When the MSC7118 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When
the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is
performed through one of two sets of pins:
Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot
Program” chapter of the MSC711x Reference Manual.
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