- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1931 > KS8001S TR (Micrel Inc)TXRX 10/100 LINKMD 3.3V 48-SSOP PDF資料下載
參數(shù)資料
| 型號： | KS8001S TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| 標準包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | KS8001L-EVAL-ND - EVAL KIT EXPERIMENTAL KS8001L |
| 其它名稱： | KS8001STR KS8001STR-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
KS8001
Micrel
May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
KS8001
MICREL CONFIDENTIAL. DO NOT DISTRIBUTE.
18
CRS
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
X
0
RX_ER
from
previous
frame
Speed
0=10Mbit
1=100Mbit
Duplex
0=Half
1=Full
Link
0=Down
1=Up
Jabber
0=OK
1=Error
Upper
Nibble
0=invalid
1=valid
False
Carrier
Detected
1
X
1
One Data Byte (Two MII Data Nibble)
TXD7 – 0 Encoding
Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status bit RXD0
indicates whether or not the PHY detected an error somewhere on the previous frame. Both of these bits should be valid in the
segment immediately following a frame, and should stay valid until the first data segment of the next frame begins.
When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event.
In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an elasticity FIFO
to handle any difference between the reference clock rate and the clock at the packet source. The Ethernet specification calls for
packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); however, it is not uncommon to encounter
Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore, the elasticity FIFO should be at least 27 bits * long,
filling to the half-way point before beginning valid data transfer via RX. RX_ER should be asserted if, during the reception of a frame,
this fifo overflows or underflows.
Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity FIFO. Instead,
CRS should be asserted for the time the ‘wire’ is busy receiving a frame.
Transmit Path
Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each segment
represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten segments represents a new
byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode.
Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
Transmit Sequence Diagram
TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TX_CLK
TX_SYNC
TX
Bits
Purpose
TX_EN
Transmit Enable – identical to MII
TX_ER
Transmit Error – identical to MII
TXD7-0
Encoded Data – see TXD7-0 Encoding Table
TX- Bit Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KS8001SI | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| KS8695PI | IC ARM9 W/MMU 5PORT 289-PBGA |
| KS8695PX | IC SWITCH 10/100 1PORT 289PBGA |
| KS8695X | IC SWITCH 10/100 5PORT 208PQFP |
| KS8721BLI TR | TXRX 10/100 3.3V 48-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS800A500-1800V Y40KSEA | 制造商:LIUJING 制造商全稱:LIUJING 功能描述:可控硅、晶閘管 |
| KS800A500-1800V Y40KSE | 制造商:LIUJING 制造商全稱:LIUJING 功能描述:可控硅、晶閘管 |
| KS8081 | 功能描述:IC SWITCH 10/100 3PORT 128PQFP RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS-80H | 制造商:Taiyo Electric Ind. 功能描述: |
| KS-80R | 制造商:Taiyo Electric Ind. 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。