參數(shù)資料
型號： KS8993FL
廠商： Micrel Inc
文件頁數(shù)： 18/99頁
文件大?。?/td> 0K
描述： IC CONV MED 10/100 SGL 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 管件
配用： 576-1012-ND - BOARD EVAL EXPERIMENT KS8993F
KS8993F
Micrel
August 26, 2004
Revision 1.0
- 25 -
The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the
MII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler.
The serialized data is further converted from NRZ to NRZI format, and then
transmitted in MLT3 current output.
The output current is set by an external 1% 3.01 K
resistor for the 1:1
transformer ratio.
It has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot and timing jitter.
The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
2.3.2
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data
and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The
receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust
its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation
based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for
optimization. This is an ongoing process and can self adjust against environmental changes such as temperature
variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of base line wander and improve the dynamic range.
The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the
4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
2.3.3
PLL Clock Synthesizer
The KS8993F generates 125 M
Ηz, 31.25 MHz, 25 MΗz and 10 MΗz clocks for system timing. Internal clocks are
generated from an external 25 MHz crystal or oscillator.
2.3.4
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The
scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data
stream with the same sequence at the transmitter.
2.3.5
100BASE-FX Operation and Signal Detection
100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler/de-
scrambler and MLT3 encoder/decoder are bypassed on transmission and reception.
In this mode, the auto
negotiation feature is bypassed since there is no standard that supports fiber auto negotiation, and the auto MDI/MDI-
X feature is also disabled.
For 100BASE-FX operation, the KS8993F FXSD1 (fiber signal detect) input pin is usually connected to the fiber
transceiver SD (signal detect) output pin. 100BASE-FX mode is activated when FXSD1 is greater than 1V. When
FXSD1 is between 1V and 1.8V, no fiber signal is detected and a Far-End Fault is generated if the feature is enabled.
Alternatively, FXSD1 can be tied high to force 100BASE-FX mode if the Far-End Fault feature is not used. When
FXSD1 is greater than 2.2V, the fiber signal is detected.
100BASE-FX signal detection is summarized in the following table.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KS8993FL-EVAL 功能描述:BOARD EVAL EXPERIMENT KS8993F RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板
KS8993I 功能描述:IC SWITCH 10/100 3PORT 128PQFP RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KS8993M 功能描述:IC SWITCH 10/100 3PORT 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KS8993M_11 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs
KS8993MA5 功能描述:IC SWITCH 3-PORT 10/100 128-PQFP RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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