KS8995MA
Micrel, Inc.
M9999-051305
34
May 2005
Pin #
Pin Name
PU/PD(1)
Description1)
86
SCONF1
Ipd
Dual MII configuration pin.
Pins 91, 86, 87
Switch MII
PHY [5] MII
000
Disable, Otri
001
PHY Mode MII
Disable, Otri
010
MAC Mode MII
Disable, Otri
011
PHY Mode SNI
Disable, Otri
100
Disable
101
PHY Mode MII
110
MAC Mode MII
PHY Mode MII
111
PHY Mode SNI
PHY Mode MII
87
SCONF0
Ipd
Dual MII configuration pin.
90
LED5-2
Ipu/O
LED indicator 2. Strap option: Aging setup. See “Aging” section
PU (default) = aging enable; PD = aging disable.
91
LED5-1
Ipu/O
LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY
MII output. See “Pin 86 SCONF1.”
113
PS1
Ipd
Serial bus configuration pin.
For this case, if the EEPROM is not present, the KS8995MA will start
itself with the PS[1:0] = 00 default register values .
Pin Configuration
Serial Bus Configuration
PS[1:0]=00
I2C Master Mode for EEPROM
PS[1:0]=01
Reserved
PS[1:0]=10
SPI Slave Mode for CPU Interface
PS[1:0]=11
Factory Test Mode (BIST)
114
PS0
Ipd
Serial bus configuration pin. See “Pin 113.”
128
TEST2
NC
NC for normal operation. Factory test pin.
Note:
1.
NC = No connect.
Ipd = Input w/ internal pull-down.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
Otri = Output tristated.