參數(shù)資料
型號: KSZ8041FTL TR
廠商: Micrel Inc
文件頁數(shù): 50/58頁
文件大?。?/td> 0K
描述: TXRX PHY 10/100 SGL LP 48TQFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: SMII
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8041TL/FTL
April 2007
54
M9999-042707-1.1
Reset Circuit
The following reset circuit is recommended for powering up the KSZ8041TL/FTL if reset is triggered by the power supply.
KSZ8041TL/FTL
3.3V
D1
D1: 1N4148
R 10K
C 10uF
RST#
Figure 21. Recommended Reset Circuit
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
KSZ8041TL/FTL
CPU/FPGA
3.3V
C 10uF
R 10K
RST_OUT_n
D1
D2
D1, D2: 1N4148
RST#
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
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