參數(shù)資料
型號(hào)： KSZ8041NLA3TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 4/45頁(yè)
文件大?。?/td> 0K
描述： TRANSCEIVER 10/100 32-MLF
標(biāo)準(zhǔn)包裝： 1
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，32-MLF?
供應(yīng)商設(shè)備封裝： 32-MLF?（5x5）
包裝： 帶卷 (TR)
配用： 576-1621-ND - BOARD EVALUATION FOR KSZ8041NL
Micrel, Inc.
KSZ8041NL
July 2008
12
M9999-071808-1.2
Strapping Options
Pin Number
Pin Name
Type
(1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipu/O
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
MII (default)
001
RMII
010
Reserved – not used
011
Reserved – not used
100
PCS Loopback
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1.
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case,
it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE or
PCS Loopback mode, or is not configured with an incorrect PHY Address.
相關(guān)PDF資料
PDF描述
KSZ8041NLJ TR TXRX PHY 10/100 3.3V 32MLF
KSZ8041RNL TXRX 10/100 3.3V PHY RMII 32-MLF
KSZ8041TLI TR IC ETHERNET PHY IND 48TQFP
KSZ8051MLL TR TXRX PHY 10/T100 3.3V MII 48LQFP
KSZ8051MLLI TR TXRX PHY 10/T100 3.3V MII 48LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8041NLAM 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:10Base-T/100Base-TX Physical Layer Transceiver
KSZ8041NL-AM 功能描述:1/1 Transceiver Full MII, RMII 32-MLF? (5x5) 制造商:microchip technology 系列:- 包裝:管件 零件狀態(tài):要求報(bào)價(jià) 類型:收發(fā)器 協(xié)議:MII，RMII 驅(qū)動(dòng)器/接收器數(shù):1/1 雙工:全 接收器滯后:- 數(shù)據(jù)速率:- 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，32-MLF? 供應(yīng)商器件封裝:32-MLF?（5x5） 標(biāo)準(zhǔn)包裝:60
KSZ8041NL-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 KSZ8041NL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8041NLI 制造商:Micrel Inc 功能描述:IC TXRX PHY 10/100 LV/LP 32-MLF*NIC*
KSZ8041NLI TR 功能描述:以太網(wǎng) IC Physical Layer Transceiver 10/100BASE-T/TX (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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