參數(shù)資料
型號(hào): KSZ8051MLLI TR
廠商: Micrel Inc
文件頁數(shù): 1/51頁
文件大?。?/td> 0K
描述: TXRX PHY 10/T100 3.3V MII 48LQFP
特色產(chǎn)品: KSZ8051/8031/8021 Series
標(biāo)準(zhǔn)包裝: 1
類型: PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 1.8V,2.5V,3.3V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
配用: 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL
其它名稱: 576-3888-6
KSZ8051MLL
10Base-T/100Base-TX
Physical Layer Transceiver
Data Sheet Rev. 1.0
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
July 2010
M9999-071210-1.0
General Description
The KSZ8051MLL is a single-supply 10Base-T/100Base-
TX Ethernet physical layer transceiver for transmission
and reception of data over standard CAT-5 unshielded
twisted pair (UTP) cable.
The KSZ8051MLL is a highly-integrated, compact solution.
It reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs and
by integrating a low-noise regulator to supply the 1.2V
core.
The KSZ8051MLL offers the Media Independent Interface
(MII) for direct connection with MII-compliant Ethernet
MAC processors and switches.
The KSZ8051MLL provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ8051MLL I/Os and
board. Micrel LinkMD
TDR-based cable diagnostics
permit identification of faulty copper cabling. Remote and
local loopback functions provide verification of analog and
digital data paths.
The KSZ8051MLL is available in the 48-pin, lead-free
LQFP package (See Ordering Information).
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet Transceiver
MII Interface support
Back-to-Back mode support for 100Mbps copper
repeater or media converter
MDC/MDIO Management Interface for PHY register
configuration
Programmable interrupt output
LED outputs for link, activity and speed status indication
On-chip termination resistors for the differential pairs
Baseline Wander Correction
HP Auto MDI/MDI-X for reliable detection and
correction for straight-through and crossover cables
with disable and enable option
Auto-negotiation to automatically select the highest link
up speed (10/100 Mbps) and duplex (half/full)
Power-down and power-saving modes
LinkMD TDR-based cable diagnostics for identification
of faulty copper cabling
Parametric NAND Tree support for fault detection
between chip I/Os and board.
Loopback modes for diagnostics
Single 3.3V power supply with VDD I/O options for
1.8V, 2.5V, or 3.3V
Built-in 1.2V regulator for core
Available in 48-pin (7mm x 7mm) LQFP package
____________________________________________________________________________________________________________
Functional Diagram
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