參數資料
型號: KSZ8041RNL-EVAL
廠商: Micrel Inc
文件頁數: 47/54頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8041RNL
標準包裝: 1
主要目的: 接口,以太網 PHY
嵌入式:
已用 IC / 零件: KSZ8041RNL
主要屬性: 單芯片 PHY,10BASE-T/100BASE-TX
已供物品:
相關產品: 576-3979-2-ND - IC TXRX PHY 10/100 3.3V 32MLF
576-3745-6-ND - TXRX PHY 100BASE TX 3.3V 32QFN
576-3745-1-ND - TXRX PHY 100BASE TX 3.3V 32QFN
576-3745-2-ND - TXRX PHY 100BASE TX 3.3V 32QFN
576-3623-6-ND - TXRX PHY 10-T/100-TX 3.3V 32MLF
576-3623-1-ND - TXRX PHY 10-T/100-TX 3.3V 32MLF
576-3623-2-ND - TXRX PHY 10-T/100-TX 3.3V 32MLF
576-3503-ND - TXRX 10/100 3.3V PHY RMII 32-MLF
其它名稱: 576-3863
Micrel, Inc.
KSZ8041NL/RNL
September 2010
51
M9999-090910-1.4
Reset Circuit
The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power
supply.
KSZ8041NL/RN L
3.3V
D1
D1: 1N4148
R 10K
C 10uF
RST#
Figure 19. Recommended Reset Circuit
The reset circuit in Figure 20 is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL/RNL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
KSZ8041NL/RNL
CPU/FPGA
3.3V
C 10uF
R 10K
RST_OUT_n
D1
D2
D1, D2: 1N4148
RST#
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
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