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參數(shù)資料
| 型號： | KSZ8051RNLI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 35/59頁 |
| 文件大小： | 0K |
| 描述： | TXRX PHY 10/T100 3.3V RMII 32QFN |
| 特色產(chǎn)品： | KSZ8051/8031/8021 Series |
| 標準包裝： | 1 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RMII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | 576-3889-6 |
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MCP414X/416X/424X/426X
DS22059B-page 40
2008 Microchip Technology Inc.
6.1
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
6.1.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the SDO
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
6.1.3
SDI/SDO
For device packages that do not have enough pins for
both an SDI and SDO pin, the SDI and SDO
functionality is multiplexed onto a single I/O pin called
SDI/SDO.
The SDO will only be driven for the command error bit
(CMDERR) and during the data bits of a read command
(after the memory address and command has been
received).
6.1.3.1
SDI/SDO Operation
Figure 6-2 shows a block diagram of the SDI/SDO pin.
The SDI signal has an internal “smart” pull-up. The
value of this pull-up determines the frequency that data
can be read from the device. An external pull-up can be
added to the SDI/SDO pin to improve the rise time and
therefore improve the frequency that data can be read.
Data written on the SDI/SDO pin can be at the
maximum SPI frequency.
On the falling edge of the SCK pin during the C0 bit
(see Figure 7-1), the SDI/SDO pin will start outputting
the SDO value. The SDO signal overrides the control of
the smart pull-up, such that whenever the SDI/SDO pin
is outputting data, the smart pull-up is enabled.
The SDI/SDO pin will change from an input (SDI) to an
output (SDO) after the state machine has received the
Address and Command bits of the Command Byte. If
the command is a Read command, then the SDI/SDO
pin will remain an output for the remainder of the
command. For any other command, the SDI/SDO pin
returns to an input.
FIGURE 6-2:
Serial I/O Mux Block
Diagram.
Note:
MCP41X1 Devices Only .
Note:
To support the High voltage requirement of
the SDI function, the SDO function is an
open-drain output.
Note:
Care must be take to ensure that a Drive
conflict does not exist between the Host
Controllers SDO pin (or software SDI/SDO
pin) and the MCP41x1 SDI/SDO pin (see
SDI/SDO
SDI
SDO
Control
“smart” pull-up
Open
Drain
Logic
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