參數(shù)資料
型號： KSZ8695PI
廠商： Micrel Inc
文件頁數(shù)： 22/42頁
文件大?。?/td> 0K
描述： IC ARM9 W/MMU 5PORT 289-PBGA
標準包裝： 84
系列： *
類型： *
應用： *
安裝類型： 表面貼裝
封裝/外殼： 289-PBGA
供應商設備封裝： 289-PBGA（19x19）
包裝： 托盤
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1623-ND - BOARD EVALUATION KSZ8695P-MMB
其它名稱： 576-2111
KSZ8695PI-ND
Micrel, Inc.
KS8695P
May 2006
29
M9999-051806
General Purpose I/O Pins (continued)
Pin
Name
I/O Type
(1)
Description
C15
A15
A16
PAD2
PAD1
PAD0
I/O
32-Bit PCI address and data (continued from previous page).
A6
B9
A11
D14
CBEN3
CBEN2
CBEN1
CBEN0
I/O
PCI commands and byte enable. Active low.
The PCI command and byte enable signals are multiplexed on the same pins.
During the rst clock cycle of a PCI transaction, the CBEN bus contains the
command for the transaction. The PCI transaction consists of the address phases
and one or more data phases. During the data phases of the transaction, the bus
carries the byte enable for the current data phases.
C8
PAR
I/O
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695P
generates PAR during the address phase and write data phases as a bus master
and during read data phases as a target. It checks for correct PAR during the read
data phase as a bus master, during every address phase as a bus slave, and during
write data phases as a target.
D10
FRAMEN
I/O
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase,
and deasserted before the nal transfer of the data phase of the transaction.
A9
IRDYN
I/O
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write
transaction. During a read transaction, it indicates that the master is ready to accept
data from the target. A target monitors the IRDYN signal when a data phase is
completed on any rising edge of the PCI clock when both IRDYN and TRDYN are
asserted. Wait cycles are inserted until both IRDYN and TRDYN are asserted
together.
C10
TRDYN
I/O
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
C11
DEVSELN
I/O
PCI device select signal. Active low. This signal is asserted when the KS8695P is
selected as a target during a bus transaction. When the KS8695P is the initiator of
the current bus access, it expects the target to assert DEVSELN within ve PCI bus
cycles, conrming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695P aborts the bus cycle. To meet the timing
requirement, the KS8695P asserts this signal in a medium speed decode timing.
(two bus cycles).
D7
IDSEL
I
Initialization device select. Active high. It is used as a chip select during
conguration read and write transactions.
D11
STOPN
I/O
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695P responds
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
abort the transaction.
B11
PERRN
I/O
PCI parity error signal. Active low. The KS8695P asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695P
monitors for any reported parity error on PERRN. When the KS8695P is the bus
master and a parity error is detected, the KS8695P sets error bits in the control
status registers. It completes the current data burst transaction, and then stops the
operation. After the host clears the system error, the KS8695P continues its
operation.
A10
SERRN
O
PCI system error signal. Active low. If an address parity error is detected, the
KS8695P asserts the SERRN signal two clocks after the failing address.
E4
M66EN
I
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK
is driven by an external host bridge.
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相關代理商/技術參數(shù)
參數(shù)描述
KSZ8695P-MDP-EVAL 功能描述:網(wǎng)絡開發(fā)工具 KSZ88695P-MDP Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8695P-MMB-EVAL 功能描述:網(wǎng)絡開發(fā)工具 KSZ8695P-MMB Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8695PX 功能描述:網(wǎng)絡控制器與處理器 IC Integrated Multi-Port Gateway Solution w/ Single PCI(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
KSZ8695PX-EVAL 功能描述:網(wǎng)絡開發(fā)工具 KSZ8695PX Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8695X 功能描述:網(wǎng)絡控制器與處理器 IC Integrated Multi-Port Gateway Solution (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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