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參數(shù)資料
| 型號(hào)： | KSZ8842-16MBL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 110/141頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAC CTLR 2PORT ETH 100-LFBGA |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 控制器類(lèi)型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | PCI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA |
| 供應(yīng)商設(shè)備封裝： | 100-LFBGA |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL 576-1634-ND - BOARD EVALUATION KSZ8842-16MQL |
| 其它名稱(chēng)： | 576-3076 |
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Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
70
M9999-102207-1.9
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits
are not cleared when read. The user has to write “1” to clear
Bit
Default Value
R/W
Description
15
0x0
RO
(W1C)
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link
down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
14
0x0
RO
(W1C)
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on
the MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
13
0x0
RO
(W1C)
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
12
0x0
RO
Reserved
11
0x0
RO
(W1C)
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
10
0x0
RO
Reserved
9
0x1
RO
(W1C)
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
8
0x1
RO
(W1C)
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
7
0x0
RO
(W1C)
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
6-0
-
RO
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8842-16MBL-EVAL | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16MBLI | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch + Generic (8, 16-Bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-16MBLI TR | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch + Generic (8, 16-Bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-16MQL | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-16MQL-EVAL | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 KSZ8842-16MQL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: |
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