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參數(shù)資料
| 型號(hào)： | KSZ8851SNL TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 3/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR MAC/PHY NON-PCI 32-MLF |
| 產(chǎn)品培訓(xùn)模塊： | KSZ8851 10/100 Embedded Controllers |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 接口： | 總線 |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-3293-ND - BOARD EVALUATION KSZ8851SNL |
| 其它名稱： | 576-3299-6 |
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Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
11
M9999-083109-2.0
Pin Description
Pin Number
Pin Name
Type
Pin Function
1
LED0
Opu
Programmable LED output to indicate PHY activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
LED indicators
1 defined as follows:
Chip Global Control Register: CGCR bit [9]
0 (Default)
1
LED1 (pin 32)
100BT
ACT
LED0 (pin 1)
LINK/ACT
LINK
Link (up) = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
2
PME
Opu
Power Management Event (default active low)
It is asserted (low or high depends on polarity set in PMECR register) when one of the
wake-on-LAN events is detected by KSZ8851SNL. The KSZ8851SNL is requesting the
system to wake up from low power mode.
3
INTRN
Opu
Interrupt Not
An active low signal to host CPU to indicate an interrupt status bit is set. This pin needs
an external 4.7K pull-up resistor.
4
DGND
Gnd
Digital IO ground.
5
VDD_CO1.8
P
1.8V regulator output . This 1.8V output pin provides power to pins 9 (VDD_A1.8) and 23
(VDD_D1.8) for core VDD supply.
If VDD_IO is set for 1.8V then this pin should be left floating, pins 9 (VDDA_1.8) and 23
(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 25 and 30
(VDD_IO) with appropriate filtering.
6
EED_IO
Ipd/O
In/Out Data from/to external EEPROM
Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during
power-up / reset. See “Strapping Options” section for details.
7
EESK
Opd
EEPROM Serial Clock
A 4
μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip
bus speed @ 125 MHz) serial output clock to load configuration data from the serial
EEPROM.
8
AGND
Gnd
Analog ground.
9
VDD_A1.8
P
1.8V analog power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO)
with appropriate filtering.
10
EECS
Opd
EEPROM Chip Select
This signal is used to select an external EEPROM device.
11
RXP
I/O
Physical receive (MDI) or transmit (MDIX) signal (+ differential).
12
RXM
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential).
13
AGND
Gnd
Analog ground.
14
TXP
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential).
15
TXM
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential).
16
VDD_A3.3
P
3.3V analog VDD input power supply with well decoupling capacitors.
17
ISET
O
Set physical transmits output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
18
AGND
Gnd
Analog ground.
19
RSTN
Ipu
Reset Not.
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