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參數(shù)資料
| 型號： | KSZ8851SNL TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 8/80頁 |
| 文件大小： | 0K |
| 描述： | IC CTLR MAC/PHY NON-PCI 32-MLF |
| 產(chǎn)品培訓模塊： | KSZ8851 10/100 Embedded Controllers |
| 標準包裝： | 1 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 接口： | 總線 |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應商設備封裝： | 32-MLF?（5x5） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-3293-ND - BOARD EVALUATION KSZ8851SNL |
| 其它名稱： | 576-3299-6 |
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Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
16
M9999-083109-2.0
Physical Layer Transceiver (PHY)
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion,
and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further
converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 3.01k
Ω (1%) resistor is
connected to pin 17 (ISET) for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance,
overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock
recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable.
Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to
optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming
signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and
self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder.
Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
PLL Clock Synthesizer (Recovery)
The internal PLL clock synthesizer can generate either 125MHz, 62.5MHz, 41.66MHz, or 25MHz clocks by setting the on-chip
bus control register (0x20) for KSZ8851SNL system timing. These internal clocks are generated from an external 25MHz crystal
or oscillator.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and
baseline wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates
a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at
the transmitter.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They
are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents are at least
27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a
phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels
less than 400mV or with short pulse widths to prevent noise at the RXP or RXM input from falsely triggering the decoder. When
the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851SNL decodes a data frame. The
receiver clock is maintained active during idle periods in between data reception.
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