參數(shù)資料
型號(hào)： KSZ8863FLL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 66/106頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863FLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863FLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3750-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3576-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱(chēng)： 576-3866
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 61
10.2.3
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 10-4 shows how the R/C combina-
tion is connected to the PIC16CXXX family.
FIGURE 10-4: RC OSCILLATOR MODE
10.3
Reset
The PIC16CXXX family differentiates between various
kinds of reset:
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 10-4. These bits are used in software to deter-
mine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
A simplied block diagram of the on-chip reset circuit is
shown in Figure 10-5.
The PIC16C72/CR72 have a MCLR noise lter in the
MCLR reset path. The lter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
OSC2/CLKOUT
Cext
Rext
PIC16CXXX
OSC1
Fosc/4
Internal
clock
VDD
VSS
Recommended values:
3 k
≤ Rext ≤ 100 k
Cext > 20pF
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