參數(shù)資料
型號： KSZ8863RLL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 5/106頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863RLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863RLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3752-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3578-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3868
PIC18FXX2
DS39564C-page 100
2006 Microchip Technology Inc.
9.6
Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18F4X2).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit, PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD control input
pin, RE0/RD and WR control input pin, RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, which will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 9-10:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
FIGURE 9-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Data Bus
WR LATD
RDx
Q
D
CK
EN
QD
EN
RD PORTD
Pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
or
PORTD
RD LATD
Data Latch
TRIS Latch
Q1
Q2
Q3
Q4
CS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
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