參數(shù)資料
型號(hào): KSZ8863RLL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 80/106頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8863RLL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8863RLL
已供物品:
相關(guān)產(chǎn)品: 576-3752-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3578-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱: 576-3868
PIC16C72 Series
DS39016A-page 74
Preliminary
1998 Microchip Technology Inc.
TABLE 11-2
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f
-
f, d
f
-
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1(2)
1
1(2)
1
00
0111
0101
0001
1001
0011
1011
1010
1111
0100
1000
0000
1101
1100
0010
1110
0110
dfff
lfff
0xxx
dfff
lfff
0xx0
dfff
ffff
xxxx
ffff
0000
ffff
C,DC,Z
Z
C
C,DC,Z
Z
1,2
2
1,2
1,2,3
1,2
1,2,3
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1 (2)
01
00bb
01bb
10bb
11bb
bfff
ffff
1,2
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
-
k
-
k
-
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
2
1
2
1
2
1
11
10
00
10
11
00
11
00
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
110x
1010
kkkk
0110
kkkk
0000
kkkk
0000
0110
kkkk
0100
kkkk
1001
kkkk
1000
0011
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modied as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin congured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modied or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
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